Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.
Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors. Even slower has been the increase in operating speed of memory controllers coupling processors to memory devices. The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.
In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay of several clock periods. Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices.
One approach to alleviating the memory latency problem is to use multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, a system controller or memory controller is coupled over a high speed link to several memory modules. Typically, the memory modules are coupled in a point-to-point or daisy chain architecture such that the memory modules are connected one to another in series. Thus, the memory controller is coupled to a first memory module over a first high speed link, with the first memory module connected to a second memory module through a second high speed link, and the second memory module coupled to a third memory module through a third high speed link, and so on in a daisy chain fashion.
Each memory module includes a memory hub that is coupled to the corresponding high speed links and a number of memory devices on the module, with the memory hubs efficiently routing memory requests and memory responses between the controller and the memory devices over the high speed links. Computer systems employing this architecture can have a higher bandwidth because a processor can access one memory device while another memory device is responding to a prior memory access. For example, the processor can output write data to one of the memory devices in the system while another memory device in the system is preparing to provide read data to the processor. Moreover, this architecture also provides for easy expansion of the system memory without concern for degradation in signal quality as more memory modules are added, such as occurs in conventional multi drop bus architectures.
Signals are transferred over the high speed links at very high rates, with the links being optical, radio frequency, or other suitable high speed communications media. As the data transfer rate increases, the duration for which each signal being transferred over the high speed link is valid decreases by a corresponding amount, as will be understood by one skilled in the art. More specifically, the data window or “data eye” for each of the signals decreases as the data transfer rate increases. As understood by those skilled in the art, the data eye for each of the signals defines the actual duration for which each signal is valid after timing skew, jitter, duty cycle variation, and other types of unwanted signal distortion are considered. Signal distortion can arise from a variety of sources, such as different loading on the lines of the link and the physical lengths of such lines.
In a conventional system memory, to synchronize memory devices coupled to a memory controller the controller enters an initialization or synchronization mode of operation and applies a test data pattern to the memory devices. Typically, the controller thereafter adjusts the phase of the data strobe signal relative to the signals forming the test data pattern and determines limits for phase shifts of the data strobe signal that allow the memory device to successfully capture the data signals. A phase shift within the determined limits is then selected for use during normal operation of the controller and memory device. In the conventional system memory, each memory device is coupled to the controller over a common memory bus. Conversely, in a memory hub system having a daisy-chain configuration not every memory hub is coupled directly to the controller. The controller does not directly communicate with each memory hub in a memory hub system having more than one memory hub, and therefore the controller cannot synchronize the memory hubs in the same way as in a conventional system memory.
There is a need for a system and method of synchronizing memory hubs in a system memory having a memory hub architecture.